Xilinx ISE Foundation™
Actel Libero® (IDE)
Altera Quartus® II
The Adapticom design team has decades of experience implementing FPGAs both in new designs and re-designs in which board level logic is swept into the FPGA. The team specializes in RTL based HDL designs for synthesis specific to vendor target technologies, as well as functional verification, device modeling, system level modeling and timing-signoff/verification requirements.
From a simple CPU interface design to a complex multi-million gate SOC, designs can be done in the client's choice of CAD packages in either a flat or hierarchical configuration with a mix of VHDL, Verilog, and/or schematic based modules. Adapticom has engineers available who specialize in FPGA / FPSOC design utilizing Actel, Atmel, Altera, QuickLogic & Xilinx FPGAs, as well as engineers that work "across brands" and are familiar with all families.
Adapticom engineers have extensive experience resolving FPGA performance issues such as timing issues caused by high device utilization combined with high clock speeds. Our programmers have routinely developed custom scripts to aid in regimenting design constraints, fixing module placement, analyzing routing, etc.