Revision "H", last modified 11/21/2006
VHDL Design
FPGA - DSP - Modem - Wireless - Microwave
Raleigh - Durham - RTP - Chapel Hill
VHDL Design Portfolio
VHDL Design Modules
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VHDL Design Tools
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- QPSK Demodulator
- 128-tap/32 bit precision FIR filter
- PCI/VME bridge
- Serial FPDP SERDES/MGT
- Ethernet host interface
- VHDL design of 10 Gig Ethernet
- VME bus exerciser and analyzer
- MicroBlaze soft processor
- RS422/RS485/LVDS interfaces
- VHDL design of MGT (Multi Gigabit Transceiver)
- USB host interface
- 10Gbe LAN/WAN and OTN port interface
- LAN/WAN/HDLC packet generators and receiver
- configurable LLC/SNAP fields
- MPLS tags and HDLC link negotiation
- modem used in TRuepoint™ 5000 point-to-point digital radio
- PCI core
- Cross Point Switch
- SSTL2 DDR SDRAM
- host interface design for QDR SDRAM controller
- SONET switch cross connect
- Motorola PPC 860 CPU interface
- TDM highway communications link including error correction and detection
- SOC architecture of HDTV Video Compression processor
- wireless point to point LAN
- TX/RX ATM cell processor
- ATM cell processor
- Cartesian IQ transmit modulator
- IF Filter
- Clock Synthesiser
- Modem DSP
- RX DSP Interface
- TX DSP Interface
- Nyquist filter
- MPEG2 video/audio to PCI bus encoder
- Slope Equalizer
- SONET OC48/192 overhead frame monitoring and Add/Drop processing
- Trellis module
- SPI Interface
- I2C Interface
- Video Compression Processor sub modules
- Reed-Solomon error correction
- PCMCIA\ISA bus to local INTEL i960 bus interface
- 10 Gig WAN
- OTN
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VHDL design of XAUI
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VHDL design of SFPDP
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VHDL design of IP Packet generation
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VHDL design of RF Modem design
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VHDL design of IRIG
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VHDL design of MPEG2 encoder
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VHDL design of MPEG2 decoder
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Adapticom has a long design history with several types of HDL:
- VHDL - IEEE1076-1987,1993,2002
- VHDL - IEEE1364-1995
- Verilog 2001 with PLI V2.0
- System Verilog 3.1
- SystemC
- AHDL
These and other vendor specific HDL standards targeting:
CPLD, FPGA, Gate array, Standard cell ASIC and Custom ASIC designs.
Adapticom Engineers specialize in RTL based HDL designs for synthesis
specific to vendor target technologies, as well as functional
verification, device modeling, system level modeling and
timing-signoff/verification requirements.
From a simple CPU interface design to a complex multi-million gate SOC,
designs can be done in the client's choice of CAD packages in
either a flat or hierarchical
configuration with a mix of VHDL, Verilog, and/or schematic based
modules. Adapticom has engineers available who specialize in FPGA
/ FPSOC design utilizing Actel, Altera,
& Xilinx FPGAs, as well as engineers that work "across brands" and
are
familiar with all families.
Adapticom engineers have extensive experience resolving FPGA
performance issues such as timing issues caused by high device
utilization combined with
high clock speeds. Our programmers have routinely developed
custom scripts to aid in regimenting design constraints, fixing module
placement, analyzing
routing, etc.
Adapticom services Raleigh, Durham, RTP, & Chapel Hill North Carolina, as well as the Eastern Seaboard and Continental U.S.
Adapticom provides a wide range of engineering services. Please see our
Main Page
for further information.
Comments to:
http://www.adapticom1.net/mailto
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